Active matrix substrates in which pixel electrodes are arranged in a matrix pattern are used in display devices, such as liquid crystal display devices. Liquid crystal display devices are used not only as large-size televisions, but also as small-size display devices such as display sections of portable telephones. When active matrix substrates are used as small-size display devices, those including drivers therein are used desirably.
FIG. 6 shows an equivalent circuit diagram of a liquid crystal display device 700 using a conventional active matrix substrate 600. As shown in FIG. 6, the active matrix substrate 600 includes a TFT (Thin Film Transistor) 615 provided for each pixel electrode 620, with the gate of the TFT 615 being connected to a gate bus line 605 extending in the row direction, and the source region of the TFT 615 to a source bus line 610 extending in the column direction. A gate driver 650 and a source driver 680 are provided in the peripheral region of the active matrix substrate 600, wherein the gate driver 650 applies a scanning signal voltage to the gate bus line 605, and the source driver 680 applies a data signal voltage to the source bus line 610. The gate driver 650 includes a buffer inverter 660 provided for each row of pixels.
Referring now to FIG. 7, the configuration of the conventional active matrix substrate 600 will be described. FIG. 7(a) shows a schematic plan view of the buffer inverter 660 and the vicinity thereof in the peripheral region, and FIG. 7(b) shows a schematic plan view of the pixel electrode 620 and the vicinity thereof in the display region.
As shown in FIG. 7(a), the buffer inverter 660 includes a Pch transistor section 662, and an Nch transistor section 664. A Pch transistor section 662 includes two PMOS (P-channel Metal-Oxide Semiconductor) transistors 662a and 662b, and the Nch transistor section 664 includes two NMOS (N-channel Metal-Oxide Semiconductor) transistors 664a and 664b. The transistor sections 662 and 664 each include two transistors as described above, thus increasing the driving power (output capacity). In the buffer inverter 660, transistors of the same conductivity type are arranged in the column direction (the y direction), sharing a drain region.
In the active matrix substrate 600, the gate bus line 605 extends in the row direction (the x direction) in the display region but is bent perpendicularly (in the column direction) in the vicinity of the buffer inverter 660. The source bus line 610 extends in the column direction (the y direction).
A contact portion 668 electrically connects the drain region of the transistors 662a and 662b with a region of a portion of the gate bus line 605 that is extending in the column direction, and a contact portion 669 electrically connects the drain region of the transistors 664a and 664b with another region of the portion of the gate bus line 605 that is extending in the column direction. As described above, the drain region of the transistors 662a and 662b and the drain region of the transistors 664a and 664b are electrically connected to the gate bus line 605 via the contact portions 668 and 669.
Contact portions 670a and 670b electrically connect the source regions of the transistors 662a and 662b with the high-voltage power supply, and contact portions 672a and 672b electrically connect the source regions of the transistors 664a and 664b with the low-voltage power supply. The Pch transistor section 662 and the Nch transistor section 664 described above together form a CMOS to be a buffer inverter.
As can be seen from FIG. 7, in the active matrix substrate 600, the contact portions 668 and 669 each connect a semiconductor layer 663 or 665, respectively, with the gate bus line 605 via a plurality of connecting portions 668b, 668c, 669b and 669c separated from one another. The contact portions 670a, 670b, 672a and 672b are in contact with the semiconductor layers 663 and 665 via a plurality of connecting portions 670c, 670d, 672c and 672d, respectively, separated from one another. By thus connecting two members together via a plurality of connecting portions, connection failure is suppressed even when the connection is insufficient at one connecting portion.
With active matrix substrates, there have been demands for realizing narrower bezels, and there have also been demands for placing existing components within a smaller area in the peripheral region to so as make a space for placing a new circuit for improving the functionality. In recent years, small-size display devices with a limited display area have also been required to produce a higher-definition display, and the resolution thereof has been improved by reducing the pixel size. For example, while QVGA (resolution: 320×240) display devices have been used for display sections of portable telephones, VGA (resolution: 640×480) display devices whose resolution is four times higher have been put onto the market, and it is expected that the definition will be further increased in the future.
However, when transistors of the same conductivity type are arranged in the column direction (the y direction) as are in the active matrix substrate 600 shown in FIG. 7, it is not possible to realize a small width in the y direction of a buffer inverter provided for a row of pixels, thus failing to achieve a higher definition. In view of this, transistors of the same conductivity type may be arranged in the direction in which the gate electrode extends, as disclosed in Patent Document 1, in which case the width of the buffer inverter in the y direction can be reduced as compared with a case where transistors of the same conductivity type are arranged in the direction perpendicular to the direction in which the gate electrode extends.
Referring now to FIGS. 8 and 9, the configuration of another conventional active matrix substrate 800 will be described. FIG. 8(a) shows a schematic plan view of a buffer inverter 860 and the vicinity thereof in the peripheral region, and FIG. 8(b) shows a schematic plan view of a pixel electrode 820 and the vicinity thereof in the display region. FIG. 9 shows a cross section taken along line A-A′ in FIG. 8(a).
In the active matrix substrate 800, transistors of the same conductivity type are arranged in the row direction, thus increasing the gate width (the length in the x direction) and hence the driving power, and also reducing the width of the buffer inverter 860 in the column direction (the y direction) as compared with that of the buffer inverter 660 shown in FIG. 7(a). As described above, with a reduction in the width of the buffer inverter 860 in the column direction, it is possible to reduce the pixel size and to achieve a higher-definition display.
As shown in FIG. 9, a contact portion 868 includes a flat portion 868a provided on an interlayer film 876, gate bus line connecting portions 868b, Pch drain connecting portions 868c, and Nch drain connecting portions 868d. As does the contact portion 868, a contact portion 870 includes a flat portion 870a provided on the interlayer film 876 and Pch source connecting portions 870b, and a contact portion 872 includes a flat portion 872a provided on the interlayer film 876 and Nch source connecting portions 872b. The connecting portions 868b, 868c, 868d, 870b and 872b are provided in contact holes formed in an insulating layer 874 and the interlayer film 876.
The active matrix substrate 800 is produced as follows.
First, a base coat film (not shown) is formed on an insulative substrate 861, and an amorphous silicon layer is formed thereon. The amorphous silicon layer is crystallized by laser annealing, or the like. Then, the silicon layer is patterned. Thus, island-like semiconductor layers 863 and 865 are produced. Then, a silicon oxide layer is deposited, thus forming the insulating layer 874 including gate insulating films 863i and 865i. 
Then, tantalum, tungsten, or the like, is deposited on the insulating layer 874 by a sputtering method, or the like, and is patterned. The patterning is done by dry etching for the purpose of miniaturization. By this patterning, a gate bus line 805, a storage capacitor line 825 and gate electrodes 866a and 866b are formed. As described above, the gate bus line 805, the storage capacitor line 825 and the gate electrodes 866a and 866b are produced in the same step. The layer forming the gate bus line 805, the storage capacitor line 825 and the gate electrodes 866a and 866b as described above will be referred to as a gate electrode layer.
Then, the semiconductor layers 863 and 865 are implanted with ions using the gate electrodes 866a and 866b as a mask, followed by an annealing for activation, thus forming a TFT 815. Then, silicon oxide, or the like, is deposited, and contact holes are formed therein by patterning, thus forming the interlayer film 876.
Then, aluminum, or the like, is deposited in the contact holes in the interlayer film 876 and on the interlayer film 876, and is patterned. By this patterning, a source bus line 810 and the contact portions 868, 870 and 872 are produced.
Then, silicon oxide, an organic insulating film, or the like, is deposited and patterned to form contact holes, thus forming an interlayer film (not shown) in the display region, and the pixel electrode 820 is formed on the interlayer film using ITO, or the like. The active matrix substrate 800 is produced as described above.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 9-97909